Wednesday, January 29 • 4:00 PM - 5:15 PM Pacific Time (US & Canada)
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Location: Ballroom C
Title: Panel – OIF Update on 224 Gbps & 448 Gbps Common Electrical I/O (CEI) Development
Session Handouts Available Upon Speaker Approval: 0
Description:
Power efficient, low latency high-speed electrical interfaces are required to enable next-generation equipment and applications such as High-Performance Computing supporting AI training. How can we optimize electrical interfaces to meet these conflicting requirements? A panel of OIF experts will present an update on the Common Electrical I/O (CEI) developments that are work in-progress at OIF for these next-generation architectures and applications. These experts will include lessons learned as we complete the 224 Gbps developments as well as some of the challenges the industry will face as 448 Gbps discussions get underway. OIF is driving to enable power optimization for a range of applications by developing CEI specifications that are each unique to a range of reach applications, from extremely short reaches for chip-to-chip & chip-to-optical engine (XSR) to long reaches for backplane and copper cable (LR). To further improve cost and latency OIF has projects underway for linear and retimed Tx linear Rx (RTLR) interfaces at 112 Gbps and 224 Gbps. The optimizations to enable these conflicting requirements will be challenging for OIF member companies but will keep the industry moving forward with a new generation of interoperable electrical I/O interface specifications.
Type: Panel Discussion
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