Originally Aired - Thursday, January 30 • 3:00 PM - 3:45 PM Pacific Time (US & Canada)
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Location: Ballroom C
Title: Determining the Requirements, Die vs Package vs Board: Multi-Level Power Distribution Network Design
Session Handouts Available Upon Speaker Approval: 1
Description:
System design engineers face increasingly difficult power distribution network (PDN) design targets, with varying design and hardware delivery dates for chips, packages, and PCBs. Ensuring a functional PDN under these conditions is challenging. This paper explores PDN requirements at the chip, package, and PCB levels, offering guidelines to understand tradeoffs and solutions. The paper introduces an updated target impedance methodology that varies with frequency and spatial position for shared PDNs. Two power delivery strategies are examined: single point-of-load PDNs and PDNs feeding multiple paralleled loads. The required bandwidth (BW) of the PDN response depends on the supply network location. The paper aims to correlate BW changes with major PDN components from the DC source to silicon. It highlights that impedance requirements differ across the system due to spatial filtering effects. Power integrity experts must decide whether to combine power rails or provide separate power for each device. Using a high-power processor-based server system, the paper measures and simulates power rail impedance at various PDN points. The findings offer guidelines to avoid over-designing PDNs and to understand considerations for complex multi-load power deliveries.
Type: Technical Paper Session
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