Originally Aired - Wednesday, January 29 • 11:50 AM - 12:30 PM Pacific Time (US & Canada)
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Location: Great America K
Title: LPDDR5X SI/PI simulation and evaluation challenges
Session Handouts Available Upon Speaker Approval: 0
Description:
For the extreme growth of the Data Center demand and the Autonomous Driving demand and so on, the modern larger-cale Computing Systems are required, which have drastically increased Computing Performance and requires an explosive growth of Memory Transactions. So SoCs have multiple channels of high-speed DDR Interfaces, and the Scale of SoC/PKG/PCB co-design becomes larger and larger. In order to drop such large-scale System on time to the Market, it is required to have an advanced SI/PI Timing Analysis Method to analyze the DDR Interface in a short time and with high accuracy. So Socionext developed an unique DDR SI/PI/Timing Verification Environment based on Memory Designer, through the collaboration with Keysight. In this Session, Socionext will introduce an achievement of Si/PI/Timing Verification and Correlation with Measurement of LPDDR5X-8533Mbps interface.
Type: Sponsored Session
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