Originally Aired - Thursday, January 30 • 11:15 AM - 12:00 PM Pacific Time (US & Canada)
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Location: Great America K
Title: System-Level C-PHY High-Speed Signal Integrity Analysis for Mixed and Virtual Reality Systems
Session Handouts Available Upon Speaker Approval: 0
Description:
Mixed and virtual reality (MR/VR) systems present challenging design specifications regarding form factor, weight, dense routing, and meeting EMI/EMC standards. These systems encompass an array of rigid flex printed circuit boards (RFPCs) with high-speed signals that must contend with signal degradation, impedance, and return path discontinuities, in addition to other traditional signal integrity challenges. These issues require careful design tradeoffs for key parameters such as stackup layers/zones, signal routing, and termination to ensure signal fidelity.
In this paper, we are partnering with Meta to explore a simulation methodology targeting a MIPI C-PHY interface, focusing on high-speed routing across various interconnects and transitions within an MR/VR system. The goal will be to evaluate the impact on signal integrity caused by reference plane transitions and the interconnects between different layered structures. This MR/VR system consists of six RFPCs and three interconnects that will be modeled, meshed, and extracted with Cadence’s Clarity 3D Solver and optimized with the Cadence Optimality Intelligent System Explorer. We will also investigate the Pogo Pin interconnects and the use of a “virtual ground” at adjacent low-speed GPIO control signals. The simulation results will then be utilized to validate MIPI C-PHY compliance with SystemSI. The interface compliance will consist of time-domain results such as eye diagrams that include both the passive interconnect and a time-domain stimulus. This proposed simulation methodology provides a comprehensive approach to signal integrity analysis for C-PHY interfaces.
Type: Sponsored Session
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