Originally Aired - Thursday, January 30 • 8:00 AM - 8:45 AM Pacific Time (US & Canada)
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Location: Ballroom C
Title: Innovative Layout Optimization Methodology & Via Routing Pattern to Enable UCIe-36Gbps in Organic Interposer
Session Handouts Available Upon Speaker Approval: 1
Description:
Universal-Chiplet-Interconnect-Express (UCIe) is enabling multi-die systems poised to dominate high-performance data center AI semiconductors. With market demands pushing for UCIe-36Gbps, semiconductor foundries are enhancing 2.5D/3D packaging solutions to address layout and SI-PI challenges associated with high-bandwidth multi-die systems. Feasibility analysis shows CoWoS-S technology can be used for UCIe-36Gbps without major issues. However, CoWoS-R is an excellent choice for larger SoC where it has demonstrated excellent reliability [10]. This paper presents a novel SI-PI methodology and layout optimization techniques to minimize crosstalk and achieve 36Gbps in UCIe xA64 die-to-die connections using CoWoS-R technology. Our methodology combines 2D and 3D-EM extraction, balancing accuracy, and time. We highlight the challenges of implementing a Ground-Signal-Ground (G-S-G) routing pattern within the 45µm diagonal pitch micro bump pin field of a UCIe-x64 module due to CoWoS-R constraints, such as large via enclosures and stringent trace width and spacing requirements. These constraints lead to high crosstalk and obstruct UCIe-xA64 signal fanout within the 388.8µm shoreline width. This paper explains how we overcome these challenges with a novel via fanout and routing pattern (patent-pending) that facilitates G-S-G routing within the micro bump field, decreases crosstalk, and ensures successful signal fanout at 36Gbps within the specified shoreline width.
Type: Technical Paper Session
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