Originally Aired - Wednesday, January 29 • 9:00 AM - 9:45 AM Pacific Time (US & Canada)
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Location: Ballroom E
Title: Innovative Interposer Solutions for HBM3/4 with CoWoS Technology: A Path to 12.8Gbps
Session Handouts Available Upon Speaker Approval: 1
Description:
The AI boom is driving the memory industry towards HBM4 at 12.8Gbps, doubling I/O ports from 1024 in HBM3 to 2048. Semiconductor foundries are enhancing 2.5D and 3D packaging solutions for seamless HBM3/4-to-SoC integration, addressing layout and SI-PI challenges due to increased crosstalk and loss from higher I/O counts and deeper micro bump pins. Achieving 12.8Gbps HBM3/4-to-SoC integration requires systematic optimization of layout and SI-PI aspects. This paper demonstrates an efficient SI-PI layout optimization methodology, developed alongside a novel crosstalk shielding structure (patent pending approval) that significantly reduces crosstalk, enables higher speeds for HBM3 and HBM4. Our methodology is novel because it: 1. Leverages 2D and 3D-EM tools to balance accuracy and extraction-time. 2. Characterizes the interposer with Insertion-Loss (IL), Reflection-Loss (RL), Power-Sum-Crosstalk (PSXT), and Insertion-Loss-to-Crosstalk Ratio (ICR). 3. Decomposes interposer-induced jitter into ISI, crosstalk, and rise-fall time degradation to identify the dominant channel parameter affecting EYE closure, facilitating better layout and I/O architecture optimization. This paper addresses critical industry questions for achieving 12.8Gbps by evaluating CoWoS variants (CoWoS-S/R/L), determining optimal variant, stack-up layers, and routing pattern for HBM3/4-12.8Gbps. We provide a system-level jitter budget indicating available margin at 12.8Gbps and assess the need for I/O architecture enhancements such as equalization.
Type: Technical Paper Session
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